Applying the Ideal Testing Framework to HDL Programs
Küçük Resim Yok
Tarih
2018
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
VDE Verlag GmbH
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
This paper proposes a framework for testing behavioral model of sequential circuits implemented in Hardware Description Language (HDL). The concept of Ideal Testing is applied for achieving reliability and validity of both positive and negative testing. The HDL program is first modeled by a Finite State Machine (FSM) which is then converted to a Regular Expression (RE). This RE is used to construct test sequences. For positive testing, the original (fault-free) FSM model is used, while for negative testing its mutant model(s) are used to define requirements of ideal testing in conjunction with model-based and code-based mutation testing. A demonstrating example based on a real-life-like Traffic Light Controller (TLC) validates the proposed approach and analyzes its characteristic features. © ARCS 2018.
Açıklama
Gesellschaft fur Informatik e.V. (GI);Informationstechnische Gesellschaft im VDE (ITG)
31st GI/ITG International Conference on Architecture of Computing Systems, ARCS 2018 -- 9 April 2018 through 12 April 2018 -- -- 164575
31st GI/ITG International Conference on Architecture of Computing Systems, ARCS 2018 -- 9 April 2018 through 12 April 2018 -- -- 164575
Anahtar Kelimeler
Behavioral Model, Hardware Description Language, Ideal Testing, Mutation Testing, Regular Expression, Test Generation, Traffic Light Controller
Kaynak
ARCS 2018 - 31st GI/ITG International Conference on Architecture of Computing Systems, Workshop Proceedings
WoS Q Değeri
Scopus Q Değeri
N/A
